1. Field of the Invention
The present invention relates to a data processor.
2. Related Background Art
In utilization of a cache memory, often in the past, an emphasis was placed on a read latency upon cache hit (see, for example, Japanese Patent Laid Open Pub. 1993-053909).
However, there are environments in which an emphasis is placed on the throughput of data processing more than the latency for reading from the cache, which environments had a problem in that the data processing throughput might be deteriorated when cache hit and cache misses are mixed.